1. Field of the Invention
The present invention relates to a data processing apparatus and an image processing apparatus.
Priority is claimed on Japanese Patent Application No. 2010-245479, filed Nov. 1, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
In an image processing apparatus provided in an imaging apparatus such as a still-image camera, a moving-image camera, a medical endoscope camera, or an industrial endoscope camera, a pipeline process of dividing a still image of one frame into a plurality of blocks and performing a plurality of image processing operations for each divided block is well-known. FIGS. 8A, 8B, and 8C are diagrams illustrating a block division method in the pipeline process and timings of the pipeline process in accordance with the related art. FIGS. 9A and 9B are diagrams illustrating another block division method in the pipeline process and timings of the pipeline process in accordance with the related art.
When a still image of one frame is divided into a plurality of blocks as shown in FIG. 8A, a flow of image data to be processed within each divided block is continuous, but a flow of data between different blocks is not continuous (see FIG. 8B). Thus, a sequencer, which controls the entire pipeline process, resets a range of image data to be processed in each processing module (processing unit) constituting a pipeline, or the like each time before a pipeline process of each block is started (see FIG. 8C). When image processing is controlled for each series of pipeline processes, a period of time loss in which any one of processing modules constituting the pipeline does not operate occurs during processing of blocks. The loss time in which the processing module does not operate affects a processing time of a still image of one frame.
In terms of this loss time, a ratio for a time required to process a still image of one frame is changed according to a size of a block divided to process the still image of the frame. For example, as shown in FIG. 8A, an influence of the loss time on the entire image processing is small because a ratio of a time in which image data is processed is larger than the loss time when the size of the block divided to process a still image of one frame is large, that is, when an amount of image data included in each block is large. Incidentally, as shown in FIG. 9A, a ratio of the loss time is large and largely affects a processing time of the entire image processing, when the size of the block divided to process the still image of one frame is small, that is, when the amount of image data included in each block is small.
Technology for reducing time loss in processing between blocks is disclosed, for example, in Japanese Unexamined Patent Application, First Publication No. 2010-176606. In the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-176606, an interrupt signal (process completion interrupt signal) indicating that a process by a processing module is completed is output to a sequencer for each processing module constituting the pipeline. Every time the process completion interrupt signal is input from the processing module, the sequencer individually changes settings of the processing module. Thereby, the sequencer changes the settings of the processing module every time a process of each processing module is completed, not every time processing of a divided block is started. In the technology of Japanese Unexamined Patent Application, First Publication No. 2010-176606, the time loss in processing between blocks is reduced and a speed of processing a still image of one frame is increased by the sequencer changing the settings of each processing module for every processing module as described above (see FIG. 9B).
However, even when settings change after processing of one block is completed and then processing of the next block is started in a state in which the technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-176606 is adopted, there is still a processing module having large time loss among processing modules constituting a pipeline. For example, in a direct memory access (DMA) module having access to data stored in a memory such as a dynamic random access memory (DRAM) connected to a common data bus by DMA, a loss time is changed by a size (capacity) or configuration of a buffer for temporarily storing data included in the module. FIGS. 10A, 10B, and 11 are diagrams illustrating examples of DMA modules having large time loss. FIGS. 10A and 10B are block diagrams illustrating examples of schematic configurations of DMA modules in accordance with the related art. FIG. 10A shows an input DMA module, and FIG. 10B shows an output DMA module. FIG. 11 is a timing chart illustrating an example of timings of a process of a pipeline including the DMA modules in accordance with the related art.
As shown in FIG. 10A, the input DMA module includes two buffers (buffers A and B), a DMA interface (I/F) for acquiring data stored in the DRAM via a common data bus and writing the data to one buffer, and a buffer read circuit for reading data stored in the other buffer and outputting the data to the next processing module. As shown in FIG. 10B, the output DMA module includes two buffers (buffers C and D), a buffer write circuit for writing data output from a previous processing module to one buffer, and a DMA I/F for reading data stored in the other buffer and outputting the data to the DRAM via a common data bus. The DMA modules of the configurations as shown in FIGS. 10A and 10B input and output data in the same period by alternately switching buffer operations (of writing data to one buffer and reading data from the other buffer) using the two buffers.
If technology disclosed in Japanese Unexamined Patent Application, First Publication No. 2010-176606 is adopted in the process of the pipeline including the above-described DMA modules, data is output to the next processing module, or data is output to a DRAM, when writing of data to one buffer of the two buffers is completed, as shown in FIG. 11. However, processing of the next block is started after processing of a block to be currently processed is completed in processing between blocks. Thus, until writing of data to one buffer of the two buffers is completed in processing of the next block, no data is output to the next processing module or no data is output to the DRAM. Thus, as shown in FIG. 11, a time until writing to any one buffer within the DMA modules is completed becomes a loss time in processing between blocks. This loss time also affects other processing modules constituting the pipeline.
FIGS. 12A and 12B are block diagrams illustrating other examples of schematic configurations of DMA modules in accordance with the related art. The loss time is equally applied to a configuration, which includes a plurality of buffers and inputs and outputs data in the same period by sequentially switching the buffers, for example, such as a DMA module having four buffers as shown in FIGS. 12A and 12B, as well as the DMA module including two buffers. If the capacity of each buffer included in the DMA module is large, the influence of the loss time becomes larger.